A unit cell of a DRAM includes a switching transistor and a storage capacitor, and data are stored in the storage capacitor. Therefore, unlike an SRAM or a flash memory, a DRAM loses the data stored in the cell due to a leakage current as time passes by. In order to compensate the leakage current, the data stored in the cell are rewritten at certain periods. This operation is called a refresh operation, and the cell becomes electrically connected to a sense amplifier at least once within a data retention time of each cell. Here, the sense amplifier senses/amplifies the data of the cell, and rewrites the same data into the cell, and the retention time is a time during which the data written in a cell can be retained in the cell without a refresh operation.
Refresh operations may be classified into a self refresh operation performed internally by a semiconductor memory device, and an auto refresh operation performed according to an external command of a semiconductor memory device. The self refresh operation generates an internal active signal to perform a periodic refresh operation, and uses a Temperature Compensated Self refresh Oscillator (TCSR) circuit to vary the period of an internal active signal according to the ambient temperature.
FIG. 1 is a block diagram of a known self refresh circuit.
Referring to FIG. 1, the known self refresh circuit includes a temperature signal generating unit 10 and an internal active signal generating unit 11. The temperature signal generating unit 10 is configured to receive a temperature detection signal TEMPDET including a pulse generated when the internal temperature of a semiconductor memory device is higher than 95° C., and generate a temperature signal TEMP95 that is a level signal. The internal active signal generating unit 11 is configured to output a first period signal LTCSR or a second period signal EMRS as an internal active signal PSRF according to the level of the temperature signal TEMP95. Here, the period of the first period signal LTCSR decreases with an increase in temperature, and the period of the second period signal EMRS is constant regardless of temperature. An active operation for a self refresh operation is performed whenever a pulse of the internal active signal PSRF is generated.
FIG. 2 is a timing diagram illustrating an operation of the self refresh circuit illustrated in FIG. 1.
Referring to FIG. 2, when a self refresh operation starts, a self refresh signal SREF changes to logic high level. During the self refresh operation, when the internal temperature of a semiconductor memory device increases from 94° C. to 96° C., a pulse of the temperature detection signal TEMPDE is generated. The temperature signal generating unit 10 generates the temperature signal TEMP95 that changes from logic low level to logic high level after a certain delay time period TD from the input time point of the pulse of the temperature detection signal TEMPDET.
The internal active signal generating unit 11 controls the period of the internal active signal PSRF according to the level of the temperature signal TEMP95. That is, when the temperature signal TEMP95 has a logic low level, the internal active signal generating unit 11 generates the internal active signal PSRF having the same period as the first period signal LTCSR, and when the temperature signal TEMP95 has a logic high level, the internal active signal generating unit 11 generates the internal active signal PSRF having the same period as the second period signal EMRS. Thus, the period of the internal active signal PSRF is inversely proportional to temperature in the logic low level period of the temperature signal TEMP95, and the period of the internal active signal PSRF is constant regardless of temperature in the logic high level period of the temperature signal TEMP95.
However, pulses of the internal active signal PSRF may be generated continuously around the level transition point of the temperature TEMP95 as represented by ‘X’ of FIG. 2. The pulses of the internal active signal PSRF, which are generated continuously regardless of the period, may cause a self refresh operation fail.